From:                              Usher, Nathan

Sent:                               Wednesday, September 07, 2011 11:34 AM

To:                                   Davis, Mark

Subject:                          Re: LLRF2 RCM pin usage

Attachments:                 Schematics.zip; ATT00001.htm

 

Notes/Questions: 

 

·         You didn’t mention it, but I assume that the FPGA and DSP must also be capable of driving the clock signal and that all master devices need to keep that at a high impedance state when not using the bus.  Thankfully, the Rabbit signals that provide the serial port clocks CAN be set to Input mode for this purpose.

 

            All of those FPGA/DSP pins automatically go into a high impedance state when the chip is in reset.

 



·         You state that Rab_SPI2.DSPen/Rab_SPi2.FPGAen can be driven (low, I assume, from the rest of your explanation) by the Rabbit or the DSP/FPGA.  I assume that means the Rabbit should either set them to Input mode or open-drain output mode (an option for Parallel Port D signals).

            They should be set to open-drain output mode.



 

·         I assume that reading from their respective ROMs is the ONLY thing the DSP and FPGA do with the SPI2 interface, that they only do this after they are reset, and it is up to the Rabbit to ensure they don’t try to do this at the same time.  Once the Rabbit is holding both PROG_B and /DSP_RESET high, the Rabbit has no control over what happens on the SPI2 bus.  So it would be up to the FPGA and the DSP to coordinate any additional (possibly conflicting) activities on their own.

 

            The FPGA will only use the SPI2 bus immediately after it is reset.  The DSP will use the bus after reset, but it will also use it to store/read calibration values, so it needs to have control of the bus during normal operation.



 

And last but not least:

 

·         Could you send me a copy of each of the schematic pages in PDF format?

 

            I've attached them.